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19-1866; Rev 0; 12/00
MAX3950 Evaluation Kit
General Description
The MAX3950 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3950 10Gbps, 1:16 deserializer with low-voltage differential signal (LVDS) outputs. All components necessary to interface with 3.3V CML inputs and LVDS outputs are included on the EV kit. o +3.3V Single Supply o 9.95Gbps/10.7Gbps Evaluation o Fully Assembled and Tested Surface-Mount Board
Features
Evaluates: MAX3950
Component List
DESIGNATION C1, C10-C13 C2, C6-C9, C14-C17 C3 C4 QTY 5 DESCRIPTION 1000pF 10% ceramic capacitors (0402) Murata GRM36X7R102K050A 0.01F 10% ceramic capacitors (0402) Murata GRM36X7R103K016A 33F 10%, 10V min tantalum capacitor, AVX TAJC336K035 2.2F 10%, 16V min tantalum capacitor, AVX TAJC225K016 0.1F 10% ceramic capacitor (0603) Murata GRM39X7R104K016A SMB connectors (PC mount) SMA connectors (edge mount) Test points Not installed 2 x10 header (0.1in center) 56nH inductor Coilcraft 0805HS-560TKBC Not installed MAX3950EGK 68-pin QFN MAX3950 EV kit circuit board MAX3950 data sheet MAX3950 EV kit data sheet SUPPLIER AVX Murata PART MAX3950EVKIT
Ordering Information
TEMP. RANGE -40C to +85C IC-PACKAGE 68 QFN
9
1 1
C5 J1, J2, J7-J38 J3-J6 J39, J40 J41-J46 J47 L1 R1-R17 U1 None None None
1 34 4 2 6 1 1 17 1 1 1 1
Component Suppliers
PHONE 843-448-9411 770-684-7821 FAX 843-626-3123 --
Note: Please indicate that you are using the MAX3950 when contacting the suppliers.
________________________________________________________________ Maxim Integrated Products
1
For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
MAX3950 Evaluation Kit Evaluates: MAX3950
Detailed Description
The MAX3950 EV kit simplifies evaluation of the MAX3950 1:16 deserializer. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with 3.3V CML inputs and LVDS outputs. Transmission line test structures are included on the evaluation board to allow for measurement of signal loss and dispersion of clock and data signals at 10GHz.
Shunt Configuration of J47
The 2 10 header on J47 should be shunted as shown in Figure 1. Other jumper arrangements will cause the IC to operate erroneously.
Applications information
Connecting LVDS Outputs to 50 Oscilloscope Inputs
To monitor LVDS signals with 50 oscilloscope inputs, set the inputs of the oscilloscope to "AC coupling" or place a DC block in series with each output. If you are observing only one output with a 50 probe, balance the complementary output with a DC block and a 50 terminator to ground.
Figure 1. Shunt Arrangement for J47
J47
Connecting LVDS Outputs to HighImpedance Oscilloscope Inputs
To monitor LVDS signals with high-impedance oscilloscope inputs, install 100 0402 resistors on locations R1 through R17. Note that this does not provide as good a termination scheme as using the 50 inputs on an oscilloscope and the resulting output will be degraded.
Layout Consideration
The MAX3950's performance can be greatly affected by circuit-board layout and design. Use good high-frequency design techniques, including minimizing ground inductances and using fixed-impedance transmission lines on the data and clock signals.
Exposed Pad Package
The 68-pin QFN package with exposed pad incorporates features that provide a very low thermal-resistance path for heat removal from the IC--either to a PC board or to an external heatsink. The MAX3950's exposed pad must be soldered directly to a ground plane with good thermal conductance.
2
_______________________________________________________________________________________
J38
J37
J36
J35
J34
J33
J32
J31
J30
J29
VCC VCC J27
Vcc
Vcc
GND
Vcc
GND
GND
PD11-
PD14-
PD13-
PD12-
PD11+
PD14+
PD13+
PD12+
PD10+
PD10-
GND
PD0+
GND
PD0-
PD1-
PD1+
PD2-
PD2+
Vcc
GND
PD3
PD3+
PD4-
PD4+
Vcc
Vcc
GND
18
19 20
21
22
23
24 25
26
27 28
29
30
31
32
33
34
VCC VCC
J9
J10
J11
J12
J13
J14
J15
J16
J17
GND
Figure 2. MAX3950 EV Kit Schematic
68 56 J28 67 66 65 64 63 62 61 60 59 58 57 55 54 53 52 1 GND GND PD15PD9+ PD9PD8+ PD8PD7+ 45 44 43 VCC J21 J22 42 GND PD6+ PD6PD5+ PD5Vcc GND GND 40 39 38 37 36 35 VCC J19 J20 41 46 J24 47 48 J23 PD15+ GND Vcc SD+ SDPD7Vcc Vcc 49 Vcc VCC J26 50 GND 2 3 4 5 VCC 7 8 C16 0.01F VCC 10 C15 0.01F 11 SCLKVcc GND PCLKPCLK+ GND GND VCC 13 14 15 16 17 12 C14 0.01F SCLK+ 9 C17 J4 0.01F 6 51 J25
J1
J2
J3
U1 MAX3950
J5
J6
J7
J8
J18
C10 1000pF J40 VCCIN C3 33F C4 2.2F L1 C1 C5 56nH 0.1F 1000pF
C11 1000pF
C12 1000pF
C13 1000pF
VCC
GNDIN J39
C2 0.01F
C6 0.01F
C7 0.01F
C80 0.01F C9 0.01F
Evaluates: MAX3950
_______________________________________________________________________________________
MAX3950 Evaluation Kit
3
MAX3950 Evaluation Kit Evaluates: MAX3950
1.0"
Figure 3. MAX3950 EV Kit PC Board Layout--Solder Side
1.0"
Figure 4. MAX3950 EV Kit PC Board Layout--Power Plane 4 _______________________________________________________________________________________
MAX3950 Evaluation Kit Evaluates: MAX3950
1.0"
Figure 5. MAX3950 EV Kit PC Board Layout--Ground Plane
1.0"
Figure 6. MAX3950 EV Kit PC Board Layout--Component Side _______________________________________________________________________________________ 5
MAX3950 Evaluation Kit Evaluates: MAX3950
1.0"
Figure 7. MAX3950 EV Kit Component Placement Guide--Component Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 ______________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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